Data transfer networks include network elements such as, for example, routers, switches, and terminal devices which communicate with each other via data transfer links between the network elements. In many data transfer networks, there is a need to achieve synchronization between clock signals prevailing at various network elements of a data transfer network. The network elements can be configured to constitute master-slave pairs in order to distribute timing information within a data transfer network. Each slave network element controls its clock signal generator so that a reference clock signal prevailing at the corresponding master network element is regenerated in the slave network element on the basis of timing messages transferred from the master network element to the slave network element. The timing messages can be time-stamps contained by protocol data units “PDU” that can be, for example, data packets or data frames. Each time-stamp indicates the instantaneous time value at the transmission moment of the respective protocol data unit relating to the time-stamp under consideration, where the time value is based on the reference clock signal available at the master network element. It is also possible that the timing messages are timing packets or frames that are transmitted so that the time interval between transmission moments of two successive timing packets or frames is constant or otherwise known, when being measured with the reference clock signal available at the master network element. It is also possible that one or more time-stamps indicating the transmission moments of one or more timing messages are transferred in one or more data packets or frames transmitted after the one or more timing messages.
In many cases, the synchronization between network elements is accomplished as phase synchronization in which phase-error indicators are formed on the basis of reception moments of the timing messages transmitted in accordance with the reference clock signal, and a phase-controlled clock signal is controlled in accordance with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal. The phase-controlled clock signal is, however, susceptible to disturbances caused by the transfer delay variation of the timing messages. Thus, the weakness of this approach is that it tends to over-react to certain transfer delay variation characteristics. For example, 24 hours network loading patterns and/or large changes in the delay variation may cause problems in certain technologies such as, for example, asymmetric digital subscriber loops “ADSL”, microwave radios, and Gigabit passive optical networks “GPON”.
In conjunction with certain applications, e.g. the mobile 3rd generation “mobile 3G” and the succeeding Long Term Evolution “LTE” technologies, there is no phase error accumulation limit, thus phase synchronization is not an absolute requirement but the frequency synchronization is sufficient. On the other hand, modern oven controlled crystal oscillators “OCXO” are capable of producing a stable clock signal and also the cost/performance ratio of OCXOs is continuously improving. Therefore, instead of using the phase synchronization that is susceptible to disturbances caused by the transfer delay variation, a better result can be achieved by using a high-quality OCXO and frequency synchronization with a sufficiently large update interval that the adverse effect of the transfer delay variation can be reduced.
The following notations and assumptions are made in order to illustrate the challenges related to the frequency synchronization. We assume that the frequency fs of a slave clock signal is fm+εfm, where is fm the frequency of the reference clock signal and ε is the relative frequency error. Furthermore, we assume that the time ts measured with the slave clock signal is θ when the time tm measured with the reference clock signal is zero. Hence, if the relative frequency error ε is assumed to be constant over time, we get:ts=(1+ε)tm+θ.  (1)
A first timing message TM1 is transmitted from the master network element when tm=Tm1. TM1 experiences a transfer delay that is d1 when measured with the reference clock signal. Hence, TM1 arrives at the slave when tm=Tm1+d1. On the basis of Eq. (1), at this moment ts=(1+ε)(Tm1+d1)+θ. Hence, the arrival time at the slave is Ts1=(1+ε)(Tm1+d1)+θ when measured with the slave clock signal. A second timing message TM2 is transmitted from the master network element when tm=Tm2. TM2 experiences a transfer delay that is d2 when measured with the reference clock signal. Hence, the arrival time at the slave is Ts2=(1+ε)(Tm2+d2)+θ when measured with the slave clock signal.
The time interval measured with the reference clock signal between the transmission moments of TM1 and TM2 is Tm2−Tm1. The time interval measured with the slave clock signal between the reception moments of TM1 and TM2 is:Ts2−Ts1=(1+ε)(Tm2+d2)+θ−((1+ε)(Tm1+d1)+θ)=(1+ε)(Tm2−Tm1)+(1+ε)(d2−d1).  (2)
The slave network element is aware of Tm2−Tm1 because the values Tm1 and Tm2 can be transferred from the master network element to the slave network element as time-stamps or, if the timing messages are transmitted at a constant or otherwise predetermined rate, the slave network element is able to form estimates for the values Tm1 and Tm2 and the unknown constant portion of the estimates gets cancelled when calculating the difference Tm2−Tm1. Hence, the slave network element is able to calculate the following quantity:(Ts2−Ts1)−(Tm2−Tm1)=ε(Tm2−Tm1)+(d2−d1)+ε(d2−d1).  (3)
This quantity can be used for adjusting the frequency of the slave clock signal if ε(Tm2−Tm1)>>(d2−d1)+ε(d2−d1). The relative frequency errors can be for example 10−8 . . . 10−7 and Tm2−Tm1 can be for example about 3×104 s. Hence, ε(Tm2−Tm1) can be 3×10−4 . . . 10−3 s. The timing messages TM1 and TM2 should be selected to be such timing messages that the absolute value of the difference between the transfer delays d2−d1 is at most about e.g. a third of the absolute value of ε(Tm2−Tm1), i.e. |d2−d1|<10−4 . . . 10−3 s. Hence, the timing messages TM1 and TM2 should be two such timing messages which have experienced a substantially similar transfer delay from the master network element to the slave network element. Delay estimates based on the frequency-controlled slave clock signal are not suitable for finding the timing messages which have experienced a substantially similar transfer delay, because for example estimates based on the slave clock signal for the delays experienced by TM1 and TM2 are:Ts1−Tm1=d1+εd1+εTm1+θ, andTs2−Tm2=d2+εd2+εTm2+θ,  (4)where Ts1 and Ts2 are measured with the slave clock signal. Thus, the estimated delays comprise cumulated error components εTm1 and εTm2 that are proportional to the prevailing times Tm1 and Tm2 at the transmission moments of the corresponding timing messages TM1 and TM2.
US2009052431 discloses a method where the two timing messages which have experienced a substantially similar transfer delay are selected to be a first timing message that has, from among timing messages received within a first time window, the smallest estimated transfer delay and a second timing message that has, from among timing messages received within a second time window, the smallest estimated transfer delay. The method is based on the assumption that the minimum transfer delay from the master network element to the slave network element remains constant over time. This assumption is, however, not valid for example in a situation where a change in the routing conditions between the master and slave network elements has taken place. The time period between the timing messages used for the frequency control can be even 24 hours or more, and changes of the kind mentioned above are possible within such a long time period.